|
1 // Copyright (c) 1995-2009 Nokia Corporation and/or its subsidiary(-ies). |
|
2 // All rights reserved. |
|
3 // This component and the accompanying materials are made available |
|
4 // under the terms of the License "Symbian Foundation License v1.0" |
|
5 // which accompanies this distribution, and is available |
|
6 // at the URL "http://www.symbianfoundation.org/legal/sfl-v10.html". |
|
7 // |
|
8 // Initial Contributors: |
|
9 // Nokia Corporation - initial contribution. |
|
10 // |
|
11 // Contributors: |
|
12 // |
|
13 // Description: |
|
14 // e32\include\cpudefs.h |
|
15 // |
|
16 // |
|
17 |
|
18 /** |
|
19 @file |
|
20 @internalTechnology |
|
21 */ |
|
22 |
|
23 #ifndef __CPUDEFS_H__ |
|
24 #define __CPUDEFS_H__ |
|
25 |
|
26 #ifdef __ARMCC__ |
|
27 #define __ARM_ASSEMBLER_ISA__ 4 // "Instruction not supported on targeted CPU :(" |
|
28 #else |
|
29 #define __ARM_ASSEMBLER_ISA__ 4 |
|
30 #endif |
|
31 |
|
32 // Should really have been __CPU_CORTEX_A8__ instead of __CPU_CORTEX_A8N__ |
|
33 #ifdef __CPU_CORTEX_A8N__ |
|
34 #undef __CPU_CORTEX_A8__ |
|
35 #define __CPU_CORTEX_A8__ |
|
36 #endif |
|
37 |
|
38 // |
|
39 // Supported CPUs |
|
40 // |
|
41 |
|
42 #ifdef __MARM__ |
|
43 |
|
44 // FIXME: Nasty hack to get ARM SMP going |
|
45 #if defined(__SMP__) && !defined(__CPU_ARMV7) |
|
46 #undef __CPU_ARM11MP__ |
|
47 #define __CPU_ARM11MP__ |
|
48 #endif |
|
49 |
|
50 #if defined(__CPU_ARM710T__) |
|
51 #define __CPU_ARMV4T |
|
52 |
|
53 #elif defined(__CPU_ARM720T__) |
|
54 #define __CPU_ARMV4T |
|
55 |
|
56 #elif defined(__CPU_SA1__) |
|
57 #define __CPU_ARMV4 |
|
58 |
|
59 #elif defined(__CPU_ARM920T__) |
|
60 #define __CPU_ARMV4T |
|
61 |
|
62 #elif defined(__CPU_ARM925T__) |
|
63 #define __CPU_ARMV4T |
|
64 |
|
65 #elif defined(__CPU_XSCALE__) |
|
66 #define __CPU_ARMV5T |
|
67 #define __ENHANCED_DSP_INSTRUCTIONS |
|
68 |
|
69 #elif defined(__CPU_ARM926J__) |
|
70 #define __CPU_ARMV5T |
|
71 #define __ENHANCED_DSP_INSTRUCTIONS |
|
72 #define __CPU_HAS_JAZELLE |
|
73 |
|
74 #elif defined(__CPU_ARM1136__) |
|
75 #define __CPU_ARMV6 |
|
76 |
|
77 #elif defined(__CPU_ARM1176__) |
|
78 #define __CPU_ARMV6 |
|
79 |
|
80 #elif defined(__CPU_ARM11MP__) |
|
81 #define __CPU_ARMV6 |
|
82 #define __CPU_ARM_HAS_WFI |
|
83 #define __CPU_ARM_HAS_WFE_SEV |
|
84 |
|
85 #elif defined(__CPU_CORTEX_A8__) |
|
86 #define __CPU_ARMV7 |
|
87 |
|
88 #elif defined(__CPU_CORTEX_A9__) |
|
89 #define __CPU_ARMV7 |
|
90 |
|
91 #elif defined(__CPU_GENERIC_ARM4__) |
|
92 #define __CPU_ARMV4 |
|
93 |
|
94 #else |
|
95 // #error Unsupported CPU |
|
96 #define __CPU_UNKNOWN |
|
97 #endif |
|
98 |
|
99 #endif // __MARM__ |
|
100 |
|
101 |
|
102 |
|
103 // Macros for emitting single bytes of machine code |
|
104 #ifdef __CW32__ |
|
105 # define BYTE(x) _asm byte x |
|
106 #elif __GCC32__ |
|
107 # define BYTE(x) asm(".byte "#x); |
|
108 #else |
|
109 # define BYTE(x) _asm _emit x |
|
110 #endif |
|
111 |
|
112 |
|
113 // thiscall is different on GCC |
|
114 #ifdef __GCC32__ |
|
115 #define THISCALL_PROLOG0() asm("mov ecx,[esp+4]"); |
|
116 #define THISCALL_PROLOG1() asm("mov ecx,[esp+4] \n mov eax,[esp+8] \n mov [esp+4],eax"); |
|
117 #define THISCALL_PROLOG2() asm("mov ecx,[esp+4] \n mov eax,[esp+8] \n mov [esp+4],eax \n mov eax,[esp+12] \n mov [esp+8],eax"); |
|
118 #define THISCALL_PROLOG3() asm("mov ecx,[esp+4] \n mov eax,[esp+8] \n mov [esp+4],eax \n mov eax,[esp+12] \n mov [esp+8],eax \n mov eax,[esp+16] \n mov [esp+12],eax"); |
|
119 #define THISCALL_PROLOG0_BIGRETVAL() asm("mov ecx,[esp+8]"); |
|
120 #define THISCALL_PROLOG1_BIGRETVAL() asm("mov ecx,[esp+8] \n mov eax,[esp+12] \n mov [esp+8],eax"); |
|
121 #define THISCALL_EPILOG0() asm("ret"); |
|
122 #define THISCALL_EPILOG1() asm("ret"); |
|
123 #define THISCALL_EPILOG2() asm("ret"); |
|
124 #define THISCALL_EPILOG3() asm("ret"); |
|
125 #define THISCALL_EPILOG0_BIGRETVAL() asm("ret 4"); |
|
126 #define THISCALL_EPILOG1_BIGRETVAL() asm("ret 4"); |
|
127 #else |
|
128 #define THISCALL_PROLOG0() |
|
129 #define THISCALL_PROLOG1() |
|
130 #define THISCALL_PROLOG2() |
|
131 #define THISCALL_PROLOG3() |
|
132 #define THISCALL_PROLOG0_BIGRETVAL() |
|
133 #define THISCALL_PROLOG1_BIGRETVAL() |
|
134 #define THISCALL_EPILOG0() __asm ret |
|
135 #define THISCALL_EPILOG1() __asm ret 4 |
|
136 #define THISCALL_EPILOG2() __asm ret 8 |
|
137 #define THISCALL_EPILOG3() __asm ret 12 |
|
138 #define THISCALL_EPILOG0_BIGRETVAL() __asm ret 4 |
|
139 #define THISCALL_EPILOG1_BIGRETVAL() __asm ret 8 |
|
140 #endif |
|
141 |
|
142 |
|
143 // Workaround for MSVC++ 5.0 bug; MSVC incorrectly fixes up conditional jumps |
|
144 // when the destination is a C++ function. |
|
145 #if defined(__VC32__) && (_MSC_VER==1100) // untested on MSVC++ > 5.0 |
|
146 # define _ASM_j(cond,dest) _asm jn##cond short $+11 _asm jmp dest |
|
147 # define _ASM_jn(cond,dest) _asm j##cond short $+11 _asm jmp dest |
|
148 #else |
|
149 # if defined __GCC32__ |
|
150 # define _ASM_j(cond,dest) asm("j"#cond " %a0": : "i"(dest)); |
|
151 # define _ASM_jn(cond,dest) asm("jn"#cond " %a0": :"i"(dest)); |
|
152 # else |
|
153 # define _ASM_j(cond,dest) _asm j##cond dest |
|
154 # define _ASM_jn(cond,dest) _asm jn##cond dest |
|
155 # endif |
|
156 #endif |
|
157 |
|
158 |
|
159 |
|
160 //#define __MINIMUM_MACHINE_CODE__ |
|
161 |
|
162 #if defined(__WINS__) |
|
163 #define __NAKED__ __declspec( naked ) |
|
164 #ifndef __MINIMUM_MACHINE_CODE__ |
|
165 //#define __MEM_MACHINE_CODED__ |
|
166 #endif |
|
167 #define __CPU_X86 |
|
168 #endif |
|
169 |
|
170 #if defined(__X86__) |
|
171 # ifdef __GCC32__ |
|
172 # define __NAKED__ // GCC does not support naked functions on X86 |
|
173 # else |
|
174 # define __NAKED__ __declspec( naked ) |
|
175 # endif |
|
176 # ifndef __MINIMUM_MACHINE_CODE__ |
|
177 # define __MEM_MACHINE_CODED__ |
|
178 # endif |
|
179 # define __CPU_X86 |
|
180 #endif |
|
181 |
|
182 |
|
183 #if defined(__MARM__) |
|
184 #ifndef __NAKED__ // should be defined in prefix file |
|
185 #ifndef __GCCXML__ |
|
186 #define __NAKED__ __declspec( naked ) |
|
187 #else |
|
188 #define __NAKED__ |
|
189 #endif |
|
190 #endif |
|
191 #ifndef __CIA__ |
|
192 #undef __NAKED__ |
|
193 #define __NAKED__ ____ONLY_USE_NAKED_IN_CIA____ |
|
194 #endif |
|
195 #define __CPU_ARM |
|
196 |
|
197 #if defined(__MARM_ARMV5__) && !defined(__CPU_ARMV5T) |
|
198 #define __CPU_ARMV5T |
|
199 #endif |
|
200 |
|
201 #ifndef __MINIMUM_MACHINE_CODE__ |
|
202 #if !defined(__BIG_ENDIAN__) |
|
203 #define __MEM_MACHINE_CODED__ |
|
204 #define __DES_MACHINE_CODED__ |
|
205 #define __REGIONS_MACHINE_CODED__ |
|
206 #define __DES8_MACHINE_CODED__ |
|
207 #define __DES16_MACHINE_CODED__ |
|
208 #define __HEAP_MACHINE_CODED__ |
|
209 #define __REALS_MACHINE_CODED__ |
|
210 #define __COBJECT_MACHINE_CODED__ |
|
211 #define __CACTIVESCHEDULER_MACHINE_CODED__ |
|
212 #define __CSERVER_MACHINE_CODED__ |
|
213 #define __ARRAY_MACHINE_CODED__ |
|
214 #define __HUFFMAN_MACHINE_CODED__ |
|
215 #if defined(__MARM_ARM4__) || defined(__MARM_ARMI__) || defined(__MARM_THUMB__) || defined(__MARM_ARMV4__) || defined(__MARM_ARMV5__) |
|
216 #define __DES16_MACHINE_CODED_HWORD__ |
|
217 #endif |
|
218 #endif |
|
219 #endif |
|
220 #endif |
|
221 |
|
222 #ifdef __CPU_ARMV4 |
|
223 #define __CPU_64BIT_MULTIPLY |
|
224 #endif |
|
225 #ifdef __CPU_ARMV4T |
|
226 #define __CPU_THUMB |
|
227 #define __CPU_ARM_SUPPORTS_BX |
|
228 #define __CPU_64BIT_MULTIPLY |
|
229 #endif |
|
230 #ifdef __CPU_ARMV5T |
|
231 #define __CPU_THUMB |
|
232 #define __CPU_ARM_SUPPORTS_BX |
|
233 #define __CPU_ARM_SUPPORTS_BLX |
|
234 #define __CPU_64BIT_MULTIPLY |
|
235 #define __CPU_ARM_LDR_PC_SETS_TBIT |
|
236 #define __CPU_ARM_HAS_CLZ |
|
237 #define __CPU_ARM_HAS_PLD |
|
238 #endif |
|
239 #ifdef __ENHANCED_DSP_INSTRUCTIONS |
|
240 #define __CPU_ARM_HAS_MCRR |
|
241 #define __CPU_ARM_HAS_LDRD_STRD |
|
242 #endif |
|
243 #if defined(__CPU_ARMV6) || defined(__CPU_ARMV7) |
|
244 #define __CPU_THUMB |
|
245 #define __CPU_ARM_SUPPORTS_BX |
|
246 #define __CPU_ARM_SUPPORTS_BLX |
|
247 #define __CPU_64BIT_MULTIPLY |
|
248 #define __CPU_ARM_LDR_PC_SETS_TBIT |
|
249 #define __CPU_ARM_HAS_CLZ |
|
250 #define __CPU_ARM_HAS_MCRR |
|
251 #define __CPU_ARM_HAS_LDREX_STREX |
|
252 #define __CPU_ARM_HAS_LDRD_STRD |
|
253 #define __CPU_ARM_HAS_PLD |
|
254 #define __CPU_ARM_HAS_CPS |
|
255 #define __CPU_ARM_HAS_SPLIT_FSR |
|
256 #if !defined(__CPU_ARM1136__) && !defined(__CPU_ARM11MP__) |
|
257 #define __CPU_ARM_HAS_CP15_IFAR |
|
258 #endif |
|
259 #define __CPU_ARM_SUPPORTS_USER_MODE_BARRIERS |
|
260 #endif |
|
261 #if defined(__CPU_ARMV7) || (defined(__CPU_ARM1136__) && defined(__CPU_ARM1136_IS_R1__)) || defined(__CPU_ARM1176__) || defined(__CPU_ARM11MP__) |
|
262 #define __CPU_ARM_HAS_LDREX_STREX_V6K |
|
263 #define __CPU_HAS_CP15_THREAD_ID_REG |
|
264 #endif |
|
265 #if defined(__MARM_ARM4T__) || defined(__MARM_INTERWORK__) |
|
266 #define __SUPPORT_THUMB_INTERWORKING |
|
267 #endif |
|
268 #if defined(__CPU_ARMV7) |
|
269 #define __CPU_ARM_HAS_WFI |
|
270 #define __CPU_ARM_HAS_WFE_SEV |
|
271 #define __CPU_THUMB2 |
|
272 #define __CPU_SUPPORT_THUMB2EE |
|
273 #endif |
|
274 |
|
275 |
|
276 // ARM CPU macros to allow Thumb/Non-thumb builds |
|
277 #ifdef __CPU_ARM |
|
278 |
|
279 #define EXC_TRAP_CTX_SZ 10 // Nonvolatile registers + sp + pc |
|
280 |
|
281 #ifdef __SUPPORT_THUMB_INTERWORKING |
|
282 #define __JUMP(cc,r) asm("bx"#cc " "#r ) |
|
283 #ifdef __CPU_ARM_LDR_PC_SETS_TBIT |
|
284 #define __POPRET(rlist) asm("ldmfd sp!, {"rlist"pc} ") |
|
285 #define __CPOPRET(cc,rlist) asm("ldm"#cc "fd sp!, {"rlist"pc} ") |
|
286 #else |
|
287 #define __POPRET(rlist) asm("ldmfd sp!, {"rlist"lr} ");\ |
|
288 asm("bx lr ") |
|
289 #define __CPOPRET(cc,rlist) asm("ldm"#cc "fd sp!, {"rlist"lr} ");\ |
|
290 asm("bx"#cc " lr ") |
|
291 #endif |
|
292 #else |
|
293 #define __JUMP(cc,r) asm("mov"#cc " pc, "#r ) |
|
294 #define __POPRET(rlist) asm("ldmfd sp!, {"rlist"pc} ") |
|
295 #define __CPOPRET(cc,rlist) asm("ldm"#cc "fd sp!, {"rlist"pc} ") |
|
296 #endif |
|
297 |
|
298 #ifdef __CPU_ARM_SUPPORTS_BLX |
|
299 #if __ARM_ASSEMBLER_ISA__ >= 5 |
|
300 #define BLX(Rm) asm("blx r" #Rm) |
|
301 #else |
|
302 #define BLX(Rm) asm(".word %a0" : : "i" ((TInt)( 0xe12fff30 | (Rm) ))) |
|
303 #endif |
|
304 #define __JUMPL(Rm) BLX(Rm) |
|
305 #else |
|
306 #ifdef __SUPPORT_THUMB_INTERWORKING |
|
307 #define __JUMPL(Rm) asm("mov lr, pc "); \ |
|
308 asm("bx r"#Rm ) |
|
309 #else |
|
310 #define __JUMPL(Rm) asm("mov lr, pc "); \ |
|
311 asm("mov pc, r"#Rm ) |
|
312 #endif |
|
313 #endif |
|
314 |
|
315 #ifdef __MARM_THUMB__ |
|
316 #ifndef __ARMCC__ |
|
317 #define __SWITCH_TO_ARM asm("push {r0} ");\ |
|
318 asm("add r0, pc, #4 ");\ |
|
319 asm("bx r0 ");\ |
|
320 asm("nop ");\ |
|
321 asm(".align 2 ");\ |
|
322 asm(".code 32 ");\ |
|
323 asm("ldr r0, [sp], #4 ") |
|
324 #define __END_ARM asm(".code 16 ") |
|
325 #else |
|
326 #define __SWITCH_TO_ARM asm(".code 32 "); |
|
327 #define __END_ARM |
|
328 #endif |
|
329 #else |
|
330 #define __SWITCH_TO_ARM |
|
331 #define __END_ARM |
|
332 #endif |
|
333 |
|
334 #define CC_EQ 0 |
|
335 #define CC_NE 1 |
|
336 #define CC_CS 2 |
|
337 #define CC_CC 3 |
|
338 #define CC_MI 4 |
|
339 #define CC_PL 5 |
|
340 #define CC_VS 6 |
|
341 #define CC_VC 7 |
|
342 #define CC_HI 8 |
|
343 #define CC_LS 9 |
|
344 #define CC_GE 10 |
|
345 #define CC_LT 11 |
|
346 #define CC_GT 12 |
|
347 #define CC_LE 13 |
|
348 #define CC_AL 14 |
|
349 |
|
350 #ifdef __CPU_ARM_HAS_CLZ |
|
351 #if __ARM_ASSEMBLER_ISA__ >= 5 |
|
352 #define CLZ(Rd,Rm) asm("clz r" #Rd ", r" #Rm) |
|
353 #else |
|
354 #define CLZ(Rd,Rm) asm(".word %a0" : : "i" ((TInt)0xe16f0f10|((Rd)<<12)|(Rm))); |
|
355 #endif |
|
356 #define CLZcc(cc,Rd,Rm) asm(".word %a0" : : "i" ((TInt)0x016f0f10|((cc)<<28)|((Rd)<<12)|(Rm))); |
|
357 #endif |
|
358 #ifdef __CPU_ARM_HAS_MCRR |
|
359 #define MCRR(cop,opc,Rd,Rn,CRm) asm(".word %a0" : : "i" ((TInt)0xec400000|((Rn)<<16)|((Rd)<<12)|((cop)<<8)|((opc)<<4)|(CRm))); |
|
360 #define MCRRcc(cc,cop,opc,Rd,Rn,CRm) asm(".word %a0" : : "i" ((TInt)0x0c400000|((cc)<<28)|((Rn)<<16)|((Rd)<<12)|((cop)<<8)|((opc)<<4)|(CRm))); |
|
361 #define MRRC(cop,opc,Rd,Rn,CRm) asm(".word %a0" : : "i" ((TInt)0xec500000|((Rn)<<16)|((Rd)<<12)|((cop)<<8)|((opc)<<4)|(CRm))); |
|
362 #define MRRCcc(cc,cop,opc,Rd,Rn,CRm) asm(".word %a0" : : "i" ((TInt)0x0c500000|((cc)<<28)|((Rn)<<16)|((Rd)<<12)|((cop)<<8)|((opc)<<4)|(CRm))); |
|
363 #endif |
|
364 #ifdef __CPU_ARM_HAS_LDREX_STREX |
|
365 // LDREX Rd, [Rn] - load from [Rn] into Rd exclusive |
|
366 // STREX Rd, Rm, [Rn] - store Rm into [Rn] with exclusive access; success/fail indicator into Rd |
|
367 #define LDREXcc(cc,Rd,Rn) asm(".word %a0" : : "i" ((TInt)(0x01900f9f|((cc)<<28)|((Rd)<<12)|((Rn)<<16)))); |
|
368 #define STREXcc(cc,Rd,Rm,Rn) asm(".word %a0" : : "i" ((TInt)(0x01800f90|((cc)<<28)|((Rd)<<12)|(Rm)|((Rn)<<16)))); |
|
369 #if __ARM_ASSEMBLER_ISA__ >= 6 |
|
370 #define LDREX(Rd,Rn) asm("ldrex r" #Rd ", [r" #Rn "] ") |
|
371 #define STREX(Rd,Rm,Rn) asm("strex r" #Rd ", r" #Rm ", [r" #Rn "] ") |
|
372 #else |
|
373 #define LDREX(Rd,Rn) asm(".word %a0" : : "i" ((TInt)(0x01900f9f|((CC_AL)<<28)|((Rd)<<12)|((Rn)<<16)))); |
|
374 #define STREX(Rd,Rm,Rn) asm(".word %a0" : : "i" ((TInt)(0x01800f90|((CC_AL)<<28)|((Rd)<<12)|(Rm)|((Rn)<<16)))); |
|
375 #endif |
|
376 #endif |
|
377 #ifdef __CPU_ARM_HAS_LDREX_STREX_V6K |
|
378 // Byte, halfword, doubleword STREX/LDREX & unconditional CLREX |
|
379 #if __ARM_ASSEMBLER_ISA__ >= 6 |
|
380 #define LDREXB(Rd,Rn) asm("ldrexb r" #Rd ", [r" #Rn "] ") |
|
381 #define STREXB(Rd,Rm,Rn) asm("strexb r" #Rd ", r" #Rm ", [r" #Rn "] ") |
|
382 #define LDREXH(Rd,Rn) asm("ldrexh r" #Rd ", [r" #Rn "] ") |
|
383 #define STREXH(Rd,Rm,Rn) asm("strexh r" #Rd ", r" #Rm ", [r" #Rn "] ") |
|
384 #define LDREXD(Rd,Rn) asm("ldrexd r" #Rd ", [r" #Rn "] ") |
|
385 #define STREXD(Rd,Rm,Rn) asm("strexd r" #Rd ", r" #Rm ", [r" #Rn "] ") |
|
386 #else |
|
387 #define LDREXB(Rd,Rn) asm(".word %a0" : : "i" ((TInt)(0x01D00f9f|((CC_AL)<<28)|((Rd)<<12)|((Rn)<<16)))); |
|
388 #define STREXB(Rd,Rm,Rn) asm(".word %a0" : : "i" ((TInt)(0x01C00f90|((CC_AL)<<28)|((Rd)<<12)|(Rm)|((Rn)<<16)))); |
|
389 #define LDREXH(Rd,Rn) asm(".word %a0" : : "i" ((TInt)(0x01f00f9f|((CC_AL)<<28)|((Rd)<<12)|((Rn)<<16)))); |
|
390 #define STREXH(Rd,Rm,Rn) asm(".word %a0" : : "i" ((TInt)(0x01e00f90|((CC_AL)<<28)|((Rd)<<12)|(Rm)|((Rn)<<16)))); |
|
391 #define LDREXD(Rd,Rn) asm(".word %a0" : : "i" ((TInt)(0x01b00f9f|((CC_AL)<<28)|((Rd)<<12)|((Rn)<<16)))); |
|
392 #define STREXD(Rd,Rm,Rn) asm(".word %a0" : : "i" ((TInt)(0x01a00f90|((CC_AL)<<28)|((Rd)<<12)|(Rm)|((Rn)<<16)))); |
|
393 #endif |
|
394 #if !defined(__CPU_ARM1136__) || defined(__CPU_ARM1136_ERRATUM_406973_FIXED) |
|
395 #define __CPU_ARM_HAS_WORKING_CLREX |
|
396 #if __ARM_ASSEMBLER_ISA__ >= 6 |
|
397 #define CLREX asm("clrex ") |
|
398 #else |
|
399 #define CLREX asm(".word %a0" : : "i" ((TInt)(0xf57ff01f))); |
|
400 #endif |
|
401 #endif |
|
402 #endif |
|
403 #ifdef __CPU_ARM_HAS_LDRD_STRD |
|
404 #if __ARM_ASSEMBLER_ISA__ >= 5 |
|
405 #define LDRD(Rd,Rn) asm("ldrd r" #Rd ", [r" #Rn "] ") |
|
406 #define STRD(Rd,Rn) asm("strd r" #Rd ", [r" #Rn "] ") |
|
407 #else |
|
408 #define LDRD(Rd,Rn) asm(".word %a0" : : "i" ((TInt)( 0xe1c000d0 | ((Rn)<<16) | ((Rd)<<12) ))) |
|
409 #define STRD(Rd,Rn) asm(".word %a0" : : "i" ((TInt)( 0xe1c000f0 | ((Rn)<<16) | ((Rd)<<12) ))) |
|
410 #endif |
|
411 #define LDRD_ioff(Rd,Rn,off) asm(".word %a0" : : "i" ((TInt)( 0xe1c000d0 | ((Rn)<<16) | ((Rd)<<12) | (((off)&0xf0)<<4) | ((off)&0x0f) ))) |
|
412 #define STRD_ioff(Rd,Rn,off) asm(".word %a0" : : "i" ((TInt)( 0xe1c000f0 | ((Rn)<<16) | ((Rd)<<12) | (((off)&0xf0)<<4) | ((off)&0x0f) ))) |
|
413 #endif |
|
414 #if defined(__CPU_ARM_HAS_PLD) && !defined(__CPU_ARM926J__) && !defined(__CPU_UNKNOWN) // PLD is a no-op on ARM926 |
|
415 #if __ARM_ASSEMBLER_ISA__ >= 5 |
|
416 #define PLD(Rn) asm("pld [r" #Rn "] ") |
|
417 #else |
|
418 #define PLD(Rn) asm(".word %a0" : : "i" ((TInt)( 0xf5d0f000 | ((Rn)<<16) ))) |
|
419 #endif |
|
420 #define PLD_ioff(Rn, off) asm(".word %a0" : : "i" ((TInt)( 0xf5d0f000 | ((Rn)<<16) | (off) ))) // preload with immediate offset |
|
421 #define PLD_noff(Rn, off) asm(".word %a0" : : "i" ((TInt)( 0xf550f000 | ((Rn)<<16) | (off) ))) // preload with negative offset |
|
422 #else |
|
423 #define PLD(Rn) |
|
424 #define PLD_ioff(Rn, off) |
|
425 #define PLD_noff(Rn, off) |
|
426 #endif |
|
427 #ifdef __CPU_HAS_CP15_THREAD_ID_REG |
|
428 #define GET_RWRW_TID(cc,r) asm("mrc"#cc" p15, 0, "#r", c13, c0, 2 "); |
|
429 #define GET_RWRO_TID(cc,r) asm("mrc"#cc" p15, 0, "#r", c13, c0, 3 "); |
|
430 #define GET_RWNO_TID(cc,r) asm("mrc"#cc" p15, 0, "#r", c13, c0, 4 "); |
|
431 #define SET_RWRW_TID(cc,r) asm("mcr"#cc" p15, 0, "#r", c13, c0, 2 "); |
|
432 #define SET_RWRO_TID(cc,r) asm("mcr"#cc" p15, 0, "#r", c13, c0, 3 "); |
|
433 #define SET_RWNO_TID(cc,r) asm("mcr"#cc" p15, 0, "#r", c13, c0, 4 "); |
|
434 #endif |
|
435 |
|
436 #ifdef __CPU_SUPPORT_THUMB2EE |
|
437 #define GET_THUMB2EE_HNDLR_BASE(cc,r) asm("mrc"#cc" p14, 6, "#r", c1, c0, 0 ") |
|
438 #define SET_THUMB2EE_HNDLR_BASE(cc,r) asm("mcr"#cc" p14, 6, "#r", c1, c0, 0 ") |
|
439 #endif |
|
440 |
|
441 #if defined(__CPU_ARMV7) |
|
442 #define ARM_DMB_gen(opt) asm(".word %a0" : : "i" ((TInt)(0xf57ff050 | (opt) )) ) |
|
443 #define ARM_DSB_gen(opt) asm(".word %a0" : : "i" ((TInt)(0xf57ff040 | (opt) )) ) |
|
444 #define ARM_ISB_gen(opt) asm(".word %a0" : : "i" ((TInt)(0xf57ff060 | (opt) )) ) |
|
445 |
|
446 #define ARM_DMBSY ARM_DMB_gen(0xf) // full system DMB |
|
447 #define ARM_DSBSY ARM_DSB_gen(0xf) // full system DSB |
|
448 #define ARM_DMBST ARM_DMB_gen(0xe) // full system DMB, orders writes only |
|
449 #define ARM_DSBST ARM_DSB_gen(0xe) // full system DSB, orders writes only |
|
450 #define ARM_DMBSH ARM_DMB_gen(0xb) // DMB encompassing inner-shareable domain |
|
451 #define ARM_DSBSH ARM_DSB_gen(0xb) // DMB encompassing inner-shareable domain |
|
452 #define ARM_DMBSHST ARM_DMB_gen(0xa) // DMB encompassing inner-shareable domain, orders writes only |
|
453 #define ARM_DSBSHST ARM_DSB_gen(0xa) // DMB encompassing inner-shareable domain, orders writes only |
|
454 |
|
455 #define ARM_ISBSY ARM_ISB_gen(0xf) // full system ISB |
|
456 |
|
457 #define ARM_NOP asm(".word 0xe320f000 ") |
|
458 #define ARM_YIELD asm(".word 0xe320f001 ") |
|
459 |
|
460 #define __DATA_MEMORY_BARRIER__(reg) ARM_DMBSH |
|
461 #define __DATA_MEMORY_BARRIER_Z__(reg) asm("mov "#reg", #0"); ARM_DMBSH |
|
462 #define __DATA_SYNC_BARRIER__(reg) ARM_DSBSH |
|
463 #define __DATA_SYNC_BARRIER_Z__(reg) asm("mov "#reg", #0"); ARM_DSBSH |
|
464 #define __INST_SYNC_BARRIER__(reg) ARM_ISBSY |
|
465 #define __INST_SYNC_BARRIER_Z__(reg) asm("mov "#reg", #0"); ARM_ISBSY |
|
466 |
|
467 #elif defined(__CPU_ARM11MP__) |
|
468 |
|
469 #define ARM_DMB(reg) asm("mcr p15, 0, "#reg", c7, c10, 5 ") |
|
470 #define ARM_DSB(reg) asm("mcr p15, 0, "#reg", c7, c10, 4 ") |
|
471 #define ARM_ISB(reg) asm("mcr p15, 0, "#reg", c7, c5, 4 ") |
|
472 |
|
473 #define ARM_NOP asm(".word 0xe320f000 ") |
|
474 #define ARM_YIELD asm(".word 0xe320f001 ") |
|
475 |
|
476 #define __DATA_MEMORY_BARRIER__(reg) ARM_DMB(reg) |
|
477 #define __DATA_MEMORY_BARRIER_Z__(reg) asm("mov "#reg", #0"); ARM_DMB(reg) |
|
478 #define __DATA_SYNC_BARRIER__(reg) ARM_DSB(reg) |
|
479 #define __DATA_SYNC_BARRIER_Z__(reg) asm("mov "#reg", #0"); ARM_DSB(reg) |
|
480 #define __INST_SYNC_BARRIER__(reg) ARM_ISB(reg) |
|
481 #define __INST_SYNC_BARRIER_Z__(reg) asm("mov "#reg", #0"); ARM_ISB(reg) |
|
482 |
|
483 #elif defined(__CPU_ARMV6__) |
|
484 |
|
485 #define ARM_DMB(reg) asm("mcr p15, 0, "#reg", c7, c10, 5 ") |
|
486 #define ARM_DSB(reg) asm("mcr p15, 0, "#reg", c7, c10, 4 ") |
|
487 #define ARM_ISB(reg) asm("mcr p15, 0, "#reg", c7, c5, 4 ") |
|
488 |
|
489 #define __DATA_MEMORY_BARRIER__(reg) ARM_DMB(reg) |
|
490 #define __DATA_MEMORY_BARRIER_Z__(reg) asm("mov "#reg", #0"); ARM_DMB(reg) |
|
491 #define __DATA_SYNC_BARRIER__(reg) ARM_DSB(reg) |
|
492 #define __DATA_SYNC_BARRIER_Z__(reg) asm("mov "#reg", #0"); ARM_DSB(reg) |
|
493 #define __INST_SYNC_BARRIER__(reg) ARM_ISB(reg) |
|
494 #define __INST_SYNC_BARRIER_Z__(reg) asm("mov "#reg", #0"); ARM_ISB(reg) |
|
495 |
|
496 #else |
|
497 |
|
498 #define __DATA_MEMORY_BARRIER__(reg) |
|
499 #define __DATA_MEMORY_BARRIER_Z__(reg) asm("mov "#reg", #0") |
|
500 #define __DATA_SYNC_BARRIER__(reg) asm("mcr p15, 0, "#reg", c7, c10, 4 ") |
|
501 #define __DATA_SYNC_BARRIER_Z__(reg) asm("mov "#reg", #0"); asm("mcr p15, 0, "#reg", c7, c10, 4 ") |
|
502 #define __INST_SYNC_BARRIER__(reg) |
|
503 #define __INST_SYNC_BARRIER_Z__(reg) asm("mov "#reg", #0") |
|
504 |
|
505 #endif |
|
506 |
|
507 #ifdef __SMP__ |
|
508 #define __SMP_DATA_MEMORY_BARRIER__(reg) __DATA_MEMORY_BARRIER__(reg) |
|
509 #define __SMP_DATA_MEMORY_BARRIER_Z__(reg) __DATA_MEMORY_BARRIER_Z__(reg) |
|
510 #define __SMP_DATA_SYNC_BARRIER__(reg) __DATA_SYNC_BARRIER__(reg) |
|
511 #define __SMP_DATA_SYNC_BARRIER_Z__(reg) __DATA_SYNC_BARRIER_Z__(reg) |
|
512 #define __SMP_INST_SYNC_BARRIER__(reg) __INST_SYNC_BARRIER__(reg) |
|
513 #define __SMP_INST_SYNC_BARRIER_Z__(reg) __INST_SYNC_BARRIER_Z__(reg) |
|
514 #else |
|
515 #define __SMP_DATA_MEMORY_BARRIER__(reg) |
|
516 #define __SMP_DATA_MEMORY_BARRIER_Z__(reg) asm("mov "#reg", #0") |
|
517 #define __SMP_DATA_SYNC_BARRIER__(reg) |
|
518 #define __SMP_DATA_SYNC_BARRIER_Z__(reg) asm("mov "#reg", #0") |
|
519 #define __SMP_INST_SYNC_BARRIER__(reg) |
|
520 #define __SMP_INST_SYNC_BARRIER_Z__(reg) asm("mov "#reg", #0") |
|
521 #endif |
|
522 |
|
523 #ifdef __CPU_ARM_HAS_WFI |
|
524 #define ARM_WFIcc(cc) asm(".word %a0" : : "i" ((TInt)(0x0320f003 | ((cc)<<28) )) ) |
|
525 #define ARM_WFI ARM_WFIcc(CC_AL) |
|
526 #endif |
|
527 |
|
528 #ifdef __CPU_ARM_HAS_WFE_SEV |
|
529 #define ARM_WFEcc(cc) asm(".word %a0" : : "i" ((TInt)(0x0320f002 | ((cc)<<28) )) ) |
|
530 #if __ARM_ASSEMBLER_ISA__ >= 6 |
|
531 #define ARM_WFE asm("wfe ") |
|
532 #else |
|
533 #define ARM_WFE ARM_WFEcc(CC_AL) |
|
534 #endif |
|
535 #define ARM_SEVcc(cc) asm(".word %a0" : : "i" ((TInt)(0x0320f004 | ((cc)<<28) )) ) |
|
536 #if __ARM_ASSEMBLER_ISA__ >= 6 |
|
537 #define ARM_SEV asm("sev ") |
|
538 #else |
|
539 #define ARM_SEV ARM_SEVcc(CC_AL) |
|
540 #endif |
|
541 #endif |
|
542 |
|
543 #ifndef ARM_NOP |
|
544 #define ARM_NOP asm("nop ") |
|
545 #define ARM_YIELD asm("nop ") |
|
546 #endif |
|
547 |
|
548 // Support for throwing exceptions through ARM embedded assembler |
|
549 // Should only be needed user side |
|
550 #ifndef __EH_FRAME_ADDRESS |
|
551 #define __EH_FRAME_ADDRESS(reg,offset) |
|
552 #define __EH_FRAME_PUSH2(reg1,reg2) |
|
553 #define __EH_FRAME_SAVE1(reg,offset) |
|
554 #endif |
|
555 |
|
556 // StrongARM msr bug workaround: |
|
557 // (conditional msr might cause,that the next instruction is executed twice by these processors) |
|
558 #ifdef __CPU_SA1__ |
|
559 #define __MSR_CPSR_C(cc,r) \ |
|
560 asm("msr"#cc" cpsr_c," #r); \ |
|
561 ARM_NOP; |
|
562 #else // !__CPU_SA1__ |
|
563 #define __MSR_CPSR_C(cc,r) asm("msr"#cc" cpsr_c,"#r); |
|
564 #endif |
|
565 |
|
566 // Causes undefined instruction exception on both ARM and THUMB |
|
567 #define __ASM_CRASH() asm(".word 0xe7ffdeff ") |
|
568 #if defined(__GNUC__) |
|
569 #define __crash() asm(".word 0xe7ffdeff " : : : "memory") |
|
570 #elif defined(__ARMCC__) |
|
571 // RVCT doesn't let us inline an undefined instruction |
|
572 // use a CDP to CP15 instead - doesn't work on THUMB but never mind |
|
573 #define __crash() asm("cdp p15, 0, c0, c0, c0, 0 ") |
|
574 #endif |
|
575 |
|
576 #if !defined(__CPU_ARM_HAS_LDREX_STREX_V6K) |
|
577 #if defined(__CPU_ARM_HAS_LDREX_STREX) |
|
578 #define __ATOMIC64_USE_SLOW_EXEC__ |
|
579 #else |
|
580 #define __ATOMIC64_USE_FAST_EXEC__ |
|
581 #define __ATOMIC_USE_FAST_EXEC__ |
|
582 #endif |
|
583 #endif |
|
584 |
|
585 #endif // __CPU_ARM |
|
586 |
|
587 #ifdef __CPU_X86 |
|
588 #define EXC_TRAP_CTX_SZ 10 // ebx, esp, ebp, esi, edi, ds, es, fs, gs, eip |
|
589 |
|
590 // Causes exception |
|
591 #if defined(__VC32__) || defined(__CW32__) |
|
592 #define __crash() do { _asm int 0ffh } while(0) |
|
593 #else |
|
594 #define __crash() asm("int 0xff " : : : "memory") |
|
595 #endif |
|
596 |
|
597 #endif // __CPU_X86 |
|
598 |
|
599 #endif |