35 #define __PRI_LIST_MACHINE_CODED__ |
35 #define __PRI_LIST_MACHINE_CODED__ |
36 #define __FAST_SEM_MACHINE_CODED__ |
36 #define __FAST_SEM_MACHINE_CODED__ |
37 #define __FAST_MUTEX_MACHINE_CODED__ |
37 #define __FAST_MUTEX_MACHINE_CODED__ |
38 #define __NTHREAD_WAITSTATE_MACHINE_CODED__ |
38 #define __NTHREAD_WAITSTATE_MACHINE_CODED__ |
39 |
39 |
40 class TSubScheduler; |
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41 class TScheduler; |
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42 struct SFullArmRegSet; |
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43 struct ArmScu; |
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44 struct GicDistributor; |
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45 struct GicCpuIfc; |
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46 struct ArmLocalTimer; |
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47 struct ArmGlobalTimer; |
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48 |
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49 // TSubScheduler member data |
40 // TSubScheduler member data |
50 struct TSubSchedulerX |
41 #define i_ScuAddr iExtras[4] // Address of SCU (also in TScheduler) |
51 { |
42 #define i_GicDistAddr iExtras[5] // Address of GIC Distributor (also in TScheduler) |
52 TUint32 iSSXP[3]; |
43 #define i_GicCpuIfcAddr iExtras[6] // Address of GIC CPU Interface (also in TScheduler) |
53 ArmGlobalTimer* iGlobalTimerAddr; // Address of global timer registers (also in TScheduler) |
44 #define i_LocalTimerAddr iExtras[7] // Address of local timer registers (also in TScheduler) |
54 ArmScu* iScuAddr; // Address of SCU (also in TScheduler) |
45 #define i_IrqCount iExtras[8] // count of interrupts handled |
55 GicDistributor* iGicDistAddr; // Address of GIC Distributor (also in TScheduler) |
46 #define i_IrqNestCount iExtras[9] // IRQ nest count for this CPU (starts at -1) |
56 GicCpuIfc* iGicCpuIfcAddr; // Address of GIC CPU Interface (also in TScheduler) |
47 #define i_ExcInfo iExtras[10] // pointer to exception info for crash debugger |
57 ArmLocalTimer* iLocalTimerAddr; // Address of local timer registers (also in TScheduler) |
48 #define i_CrashState iExtras[11] // 0=normal, 1=this CPU faulted, 2=this CPU has received an NMI and halted |
58 volatile TUint32 iIrqCount; // count of interrupts handled |
49 #define i_AbtStackTop iExtras[12] // Top of ABT stack for this CPU, also used to point to SFullArmRegSet |
59 volatile TInt iIrqNestCount; // IRQ nest count for this CPU (starts at -1) |
50 #define i_UndStackTop iExtras[13] // Top of UND stack for this CPU |
60 TAny* iExcInfo; // pointer to exception info for crash debugger |
51 #define i_FiqStackTop iExtras[14] // Top of FIQ stack for this CPU |
61 volatile TInt iCrashState; // 0=normal, 1=this CPU faulted, 2=this CPU has received an NMI and halted |
52 #define i_IrqStackTop iExtras[15] // Top of IRQ stack for this CPU |
62 union { |
53 #define i_TimerMultF iExtras[16] // Timer frequency / Max Timer frequency * 2^32 |
63 TLinAddr iAbtStackTop; // Top of ABT stack for this CPU, also used to point to SFullArmRegSet |
54 #define i_TimerMultI iExtras[17] // Max Timer frequency / Timer frequency * 2^24 |
64 SFullArmRegSet* iRegs; |
55 #define i_CpuMult iExtras[18] // CPU frequency / Max CPU frequency * 2^32 |
65 }; |
56 #define i_LastTimerSet iExtras[20] // Value last written to local timer counter |
66 TLinAddr iUndStackTop; // Top of UND stack for this CPU |
57 #define i_TimestampError iExtras[21] // Current error in the timestamp |
67 TLinAddr iFiqStackTop; // Top of FIQ stack for this CPU |
58 #define i_MaxCorrection iExtras[22] // Maximum correction to timestamp in one go |
68 TLinAddr iIrqStackTop; // Top of IRQ stack for this CPU |
59 #define i_TimerGap iExtras[23] // Timestamp ticks taken to read and write local timer counter |
69 SRatioInv* volatile iNewCpuFreqRI; // set when CPU frequency has been changed |
60 |
70 SRatioInv* volatile iNewTimerFreqRI; // set when CPU local timer frequency has been changed |
61 #define i_Regs iExtras[12] // Alias for i_AbtStackTop |
71 SRatioInv iCpuFreqRI; // Ratio of CPU frequency to maximum possible CPU frequency |
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72 SRatioInv iTimerFreqRI; // Ratio of CPU local timer frequency to maximum possible |
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73 |
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74 TUint32 iSSXP2[36]; |
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75 TUint64 iSSXP3; // one 64 bit value to guarantee alignment |
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76 }; |
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77 |
62 |
78 // TScheduler member data |
63 // TScheduler member data |
79 struct TSchedulerX |
64 #define i_TimerMax iExtras[16] // Maximum per-CPU timer frequency (after prescaling) |
80 { |
65 |
81 TUint64 iTimerMax; // Maximum per-CPU timer frequency (after prescaling) |
66 |
82 TUint32 iSXP[1]; |
67 #define RESCHED_IPI_VECTOR 0x00 |
83 ArmGlobalTimer* iGlobalTimerAddr; // Address of global timer registers (also in TSubScheduler) |
68 #define GENERIC_IPI_VECTOR 0x01 |
84 ArmScu* iScuAddr; // Address of SCU (also in TSubScheduler) |
69 #define TRANSFERRED_IRQ_VECTOR 0x02 |
85 GicDistributor* iGicDistAddr; // Address of GIC Distributor (also in TSubScheduler) |
70 #define CRASH_IPI_VECTOR 0x03 // would really like this to be a FIQ |
86 GicCpuIfc* iGicCpuIfcAddr; // Address of GIC CPU Interface (also in TSubScheduler) |
71 #define BOOT_IPI_VECTOR 0x04 // used during boot to handshake with APs |
87 ArmLocalTimer* iLocalTimerAddr; // Address of local timer registers (also in TSubScheduler) |
72 #define RESERVED_IPI_VECTOR_1 0x05 // reserved for future kernel functionality |
88 |
73 #define RESERVED_IPI_VECTOR_2 0x06 // reserved for future kernel functionality |
89 SRatioInv iGTimerFreqRI; // ratio of global timer frequency to maximum possible |
74 #define RESERVED_IPI_VECTOR_3 0x07 // reserved for future kernel functionality |
90 TUint64 iCount0; // global timer count at last frequency change |
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91 TUint64 iTimestamp0; // timestamp at last frequency change |
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92 |
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93 TUint32 iSXP2[16]; |
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94 }; |
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95 |
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96 |
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97 #define RESCHED_IPI_VECTOR 0x00 |
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98 #define GENERIC_IPI_VECTOR 0x01 |
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99 #define TRANSFERRED_IRQ_VECTOR 0x02 |
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100 #define CRASH_IPI_VECTOR 0x03 // would really like this to be a FIQ |
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101 #define BOOT_IPI_VECTOR 0x04 // used during boot to handshake with APs |
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102 #define INDIRECT_POWERDOWN_IPI_VECTOR 0x04 // used to trigger core power down |
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103 #define RESERVED_IPI_VECTOR_1 0x05 // reserved for future kernel functionality |
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104 #define RESERVED_IPI_VECTOR_2 0x06 // reserved for future kernel functionality |
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105 #define IDLE_WAKEUP_IPI_VECTOR 0x07 // for use of Idle handler/Wakeup handler |
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106 |
75 |
107 #if defined(__CPU_ARM11MP__) |
76 #if defined(__CPU_ARM11MP__) |
108 #define TIMESLICE_VECTOR 0x1D // vector 29 is per-CPU timer interrupt |
77 #define TIMESLICE_VECTOR 0x1D // vector 29 is per-CPU timer interrupt |
109 // vector 30 is per-CPU Watchdog timer when not in watchdog mode |
78 // vector 30 is per-CPU Watchdog timer when not in watchdog mode |
110 // vector 31 is external nIRQ local interrupt pin |
79 // vector 31 is external nIRQ local interrupt pin |