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1 // Copyright (c) 1998-2009 Nokia Corporation and/or its subsidiary(-ies). |
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2 // All rights reserved. |
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3 // This component and the accompanying materials are made available |
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4 // under the terms of the License "Eclipse Public License v1.0" |
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5 // which accompanies this distribution, and is available |
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6 // at the URL "http://www.eclipse.org/legal/epl-v10.html". |
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7 // |
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8 // Initial Contributors: |
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9 // Nokia Corporation - initial contribution. |
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10 // |
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11 // Contributors: |
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12 // |
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13 // Description: |
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14 // e32\include\nkern\arm\nk_plat.h |
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15 // |
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16 // WARNING: This file contains some APIs which are internal and are subject |
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17 // to change without notice. Such APIs should therefore not be used |
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18 // outside the Kernel and Hardware Services package. |
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19 // |
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20 |
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21 /** |
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22 @file |
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23 @internalComponent |
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24 */ |
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25 |
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26 #ifndef __NK_ARM_H__ |
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27 #define __NK_ARM_H__ |
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28 #include <nk_cpu.h> |
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29 |
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30 // These macros are intended for Symbian use only. |
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31 // It may not be possible to build the kernel if any of these macros are undefined |
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32 #define __SCHEDULER_MACHINE_CODED__ |
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33 #define __DFC_MACHINE_CODED__ |
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34 #define __MSTIM_MACHINE_CODED__ |
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35 #define __PRI_LIST_MACHINE_CODED__ |
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36 #define __FAST_SEM_MACHINE_CODED__ |
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37 #define __FAST_MUTEX_MACHINE_CODED__ |
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38 #define __USER_CONTEXT_TYPE_MACHINE_CODED__ |
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39 #define __CLIENT_REQUEST_MACHINE_CODED__ |
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40 |
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41 // TScheduler member data |
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42 #define i_Regs iExtras[14] |
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43 #define i_ExcInfo iExtras[15] // pointer to exception info for crash debugger |
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44 |
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45 const TUint32 KNThreadContextFlagThumbBit0=1; |
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46 |
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47 #ifdef __CPU_ARM_USE_DOMAINS |
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48 #define DOMAIN_STACK_SPACE 4 |
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49 #else |
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50 #define DOMAIN_STACK_SPACE 0 |
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51 #endif |
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52 #ifdef __CPU_HAS_COPROCESSOR_ACCESS_REG |
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53 #define CAR_STACK_SPACE 4 |
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54 #else |
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55 #define CAR_STACK_SPACE 0 |
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56 #endif |
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57 #ifdef __CPU_HAS_VFP |
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58 #define VFP_STACK_SPACE 4 |
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59 #else |
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60 #define VFP_STACK_SPACE 0 |
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61 #endif |
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62 #ifdef __CPU_HAS_CP15_THREAD_ID_REG |
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63 #define TID_STACK_SPACE 4 |
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64 #else |
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65 #define TID_STACK_SPACE 0 |
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66 #endif |
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67 #ifdef __CPU_SUPPORT_THUMB2EE |
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68 #define THUMB2EE_STACK_SPACE 4 |
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69 #else |
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70 #define THUMB2EE_STACK_SPACE 0 |
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71 #endif |
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72 |
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73 #define EXTRA_STACK_SPACE (DOMAIN_STACK_SPACE+CAR_STACK_SPACE+VFP_STACK_SPACE+TID_STACK_SPACE+THUMB2EE_STACK_SPACE) |
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74 |
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75 #ifdef __INCLUDE_REG_OFFSETS__ |
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76 // Positions of registers on stack, relative to saved SP |
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77 #define EXTRA_WORDS (EXTRA_STACK_SPACE/4) |
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78 |
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79 #ifdef __CPU_HAS_VFP |
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80 #define SP_FPEXC ((THUMB2EE_STACK_SPACE+TID_STACK_SPACE)/4) |
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81 #endif |
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82 #ifdef __CPU_HAS_COPROCESSOR_ACCESS_REG |
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83 #define SP_CAR ((THUMB2EE_STACK_SPACE+TID_STACK_SPACE+VFP_STACK_SPACE)/4) |
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84 #endif |
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85 #ifdef __CPU_ARM_USE_DOMAINS |
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86 #define SP_DACR ((THUMB2EE_STACK_SPACE+TID_STACK_SPACE+VFP_STACK_SPACE+CAR_STACK_SPACE)/4) |
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87 #endif |
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88 |
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89 #define SP_R13U EXTRA_WORDS |
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90 #define SP_R14U (SP_R13U+1) |
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91 #define SP_SPSR (SP_R13U+2) |
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92 #define SP_R4 (SP_R13U+3) |
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93 #define SP_R5 (SP_R13U+4) |
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94 #define SP_R6 (SP_R13U+5) |
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95 #define SP_R7 (SP_R13U+6) |
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96 #define SP_R8 (SP_R13U+7) |
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97 #define SP_R9 (SP_R13U+8) |
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98 #define SP_R10 (SP_R13U+9) |
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99 #define SP_R11 (SP_R13U+10) |
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100 #define SP_PC (SP_R13U+11) |
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101 |
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102 #define SP_NEXT (SP_PC+1) // first word on stack before reschedule |
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103 #endif // __INCLUDE_REG_OFFSETS__ |
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104 |
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105 #ifdef __USER_MEMORY_GUARDS_ENABLED__ |
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106 #define USER_MEMORY_GUARD_SAVE_WORDS 2 |
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107 #else |
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108 #define USER_MEMORY_GUARD_SAVE_WORDS 0 |
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109 #endif |
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110 |
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111 class TArmContextElement; |
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112 class TArmRegSet; |
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113 |
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114 /** ARM-specific part of the nano-thread abstraction. |
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115 @internalComponent |
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116 */ |
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117 class NThread : public NThreadBase |
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118 { |
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119 public: |
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120 TInt Create(SNThreadCreateInfo& aInfo, TBool aInitial); |
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121 inline void Stillborn() |
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122 {} |
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123 |
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124 /** Value indicating what event caused thread to enter privileged mode. |
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125 @publishedPartner |
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126 @released |
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127 */ |
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128 enum TUserContextType |
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129 { |
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130 EContextNone=0, /**< Thread has no user context */ |
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131 EContextException=1, /**< Hardware exception while in user mode */ |
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132 EContextUndefined, |
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133 EContextUserInterrupt, /**< Preempted by interrupt taken in user mode */ |
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134 EContextUserInterruptDied, /**< Killed while preempted by interrupt taken in user mode */ |
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135 EContextSvsrInterrupt1, /**< Preempted by interrupt taken in executive call handler */ |
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136 EContextSvsrInterrupt1Died, /**< Killed while preempted by interrupt taken in executive call handler */ |
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137 EContextSvsrInterrupt2, /**< Preempted by interrupt taken in executive call handler */ |
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138 EContextSvsrInterrupt2Died, /**< Killed while preempted by interrupt taken in executive call handler */ |
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139 EContextWFAR, /**< Blocked on User::WaitForAnyRequest() */ |
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140 EContextWFARDied, /**< Killed while blocked on User::WaitForAnyRequest() */ |
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141 EContextExec, /**< Slow executive call */ |
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142 EContextKernel, /**< Kernel side context (for kernel threads) */ |
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143 EContextUserIntrCallback, /**< Blocked/preempted in a user callback on the way back from interrupt */ |
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144 EContextWFARCallback, /**< Blocked/preempted in a user callback on the way back from User::WFAR */ |
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145 }; |
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146 |
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147 IMPORT_C static const TArmContextElement* const* UserContextTables(); |
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148 IMPORT_C TUserContextType UserContextType(); |
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149 inline TInt SetUserContextType() |
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150 { return iSpare3=UserContextType(); } |
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151 inline void ResetUserContextType() |
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152 { if(iSpare3>EContextUndefined && iSpare3<EContextUserIntrCallback) iSpare3=EContextUndefined; } |
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153 void GetContext(TArmRegSet& aContext, TUint32& aAvailRegistersMask, const TArmContextElement* aContextTable); |
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154 void GetUserContext(TArmRegSet& aContext, TUint32& aAvailRegistersMask); |
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155 void SetUserContext(const TArmRegSet& aContext); |
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156 void GetSystemContext(TArmRegSet& aContext, TUint32& aAvailRegistersMask); |
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157 |
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158 void ModifyUsp(TLinAddr aUsp); |
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159 |
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160 #ifdef __CPU_ARM_USE_DOMAINS |
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161 TUint32 Dacr(); |
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162 void SetDacr(TUint32 aDacr); |
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163 TUint32 ModifyDacr(TUint32 aClearMask, TUint32 aSetMask); |
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164 #endif |
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165 |
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166 #ifdef __CPU_HAS_COPROCESSOR_ACCESS_REG |
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167 void SetCar(TUint32 aDacr); |
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168 #endif |
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169 IMPORT_C TUint32 Car(); |
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170 IMPORT_C TUint32 ModifyCar(TUint32 aClearMask, TUint32 aSetMask); |
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171 |
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172 #ifdef __CPU_HAS_VFP |
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173 void SetFpExc(TUint32 aDacr); |
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174 #endif |
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175 IMPORT_C TUint32 FpExc(); |
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176 IMPORT_C TUint32 ModifyFpExc(TUint32 aClearMask, TUint32 aSetMask); |
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177 }; |
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178 |
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179 |
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180 struct SArmInterruptInfo |
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181 { |
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182 TLinAddr iIrqHandler; |
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183 TLinAddr iFiqHandler; |
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184 TUint8 iCpuUsageFilter; |
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185 BTrace::THandler iBTraceHandler; |
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186 SCpuIdleHandler iCpuIdleHandler; |
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187 }; |
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188 |
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189 extern "C" SArmInterruptInfo ArmInterruptInfo; |
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190 |
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191 #endif |